Insights

Impedance is often treated as "make the trace narrower". In reality it is the result of three things working together: dielectric height, trace width and stackup. The only thing design controls is giving the fab a set of physical parameters they can calculate from.

The fab takes your files, substitutes their real stackup (dielectric thickness, copper weight) into the model, and back-calculates the width that hits your target. If dielectric height is missing from your stackup, they use a default and the width you get is not the width you wanted.

• Dielectric height in the stackup is mandatory, not optional
• State whether the target is single-ended or differential, and the tolerance
• Have the fab sign off the actual stackup, then check their calculation
• Changing laminate or stackup means recomputing impedance, not reusing old values

"Length matching" is used loosely on projects. DDR, PCIe and SerDes each want something different: some need the two legs of a pair matched, others need the whole bus matched end to end.

This definition has to be agreed between you, the board and the schematic owner. If three parties assume three different things, the board gets built to one interpretation and tested against another.

• Establish the object of matching first: pair-to-pair or bus-to-bus
• Define the tolerance and where it is measured — vias, connectors, test points
• Topology changes the answer: fly-by and tree are not the same problem
• Delay through connectors and vias counts toward total length

HDI is not "more advanced, therefore better". It solves BGA breakout density and form-factor problems, and it costs you extra process steps, lower yield and more money.

If your board just has a few more components and a finer process would solve it, HDI may not be worth it. If a 0.4mm-pitch BGA simply will not escape on four layers, HDI is the only answer.

• Try layer count first — if it escapes, skip HDI
• Minimum pad pitch and breakout space decide whether you need blind and buried vias
• Confirm stack order and via count with the fab; more orders means lower yield
• A rigid board converted to HDI means re-checking stackup and impedance

While a signal propagates, the reference plane gives its return current a path home that is as short as possible. Cut the plane and the return current takes a detour — sometimes onto a different layer.

A detour means a larger loop area, which hurts both radiated emissions and immunity. This is why plenty of boards that "mostly work" have their problems exactly where the plane is cut.

• Stitch the plane with vias wherever a high-speed signal crosses a split
• Keep plane splits away from the main return path; add stitching vias or caps
• Split planes along the direction of current, not across it
• Mark keep-out zones at splits so assembly and DFM checks catch them

A decoupling capacitor supplies instantaneous current to the chip and steers noise to ground. It only does that if it is close enough to the power pin — inductance grows with distance, and a few millimetres of trace can undo most of the benefit.

There is a second thing people forget: the capacitor's own ground path must be short too. A long ground return means the noise radiates off the plane instead of being sunk.

• Place capacitors right at the power pins, preferably on the same side of the board
• Keep the ground return short and tied to the chip's own ground reference
• Combine values in parallel to cover both low and high frequency
• Remember ESR and self-resonance; small values carry the high end

Newcomers fixate on trace length, but what affects the result far more is whether the return path is continuous. Break the return path and the signal collapses even with perfect length matching.

Making "reference plane continuity" a separate line item in design review catches more than DRC ever will.

• Check plane continuity as its own review item, not via DRC
• Protect the reference layer on both sides of high-speed routes
• Check the reference plane around every layer transition
• Draw the critical return paths and confirm them against the schematic

The value of a DFM check is not catching mistakes. It is screening out designs that are theoretically valid but cannot actually be built, using the fab's real process capability.

Trace width and spacing, drill sizes, mask dams, routed slots and panel gaps are the usual culprits. None of them violate a standard, and all of them can scrap a board.

• Get the fab's real capability chart and set your rules from it
• Mask dams, drill size, slots and tool paths are the frequent ones
• Leave room in panel gaps for clamping and process edges
• Check assembly interference too, not just the board itself

"0.1mm clearance" appears on drawings everywhere, but across different layers, fabs and processes, 0.1mm can be exactly right or completely impossible.

What matters is which layer, which process, and whether this particular fab can do it. Saying those three things is far more useful than writing a number.

• State width and spacing per layer, not as one blanket rule
• Attach the process type — outer, inner, mask, legend
• The fab's capability governs; the standard is only a floor
• Run a DFM confirmation round with any new fab

The first rule of an antenna region is that no metal, trace, silkscreen or copper pour may exist on any layer below it. Plenty of designs clear the top layer and leave copper on the inner and bottom layers.

Second is the feed line. Its impedance, length and surroundings all affect radiation efficiency, and those problems cannot be seen on the layout — they need simulation or measurement.

• Keep-out means all layers, not just the top
• No metal parts or structure in the antenna neighbourhood
• Route the feed to impedance and verify by simulation
• Leave room for a tunable matching network to make tuning practical

When a board comes back and does not work, the cause is usually not design ability. It is that nobody told the designer what the mechanical parts actually look like within tolerance.

Connector mating positions, screw positions, board-to-enclosure clearance — all of these look right on a drawing and can still fail once real tolerances stack up.

• Check against the physical parts, not only the CAD
• Walk through mating height, insertion direction and mechanical interference
• Write board thickness, enclosure clearance and hole positions into the constraints
• Let assembly attend design review — far cheaper than a respin